library verilog;
use verilog.vl_types.all;
entity dbg_registers is
    generic(
        Tp              : integer := 1
    );
    port(
        DataIn          : in     vl_logic_vector(31 downto 0);
        DataOut         : out    vl_logic_vector(31 downto 0);
        Address         : in     vl_logic_vector(4 downto 0);
        RW              : in     vl_logic;
        \Access\        : in     vl_logic;
        Clk             : in     vl_logic;
        Bp              : in     vl_logic;
        Reset           : in     vl_logic;
        RiscStall       : out    vl_logic;
        RiscReset       : out    vl_logic
    );
end dbg_registers;
